The field of the invention is in the arrangement of the signal paths in charge-coupled-devices.
In prior art devices difficulty has been encountered in providing reliable operation of the refresh-turn circuits coupling adjacent shift registers due to the extremely limited space available in which to position the necessary structure of the refresh-turn circuit which must redefine the signal-logic levels and simultaneously perform a 180.degree. turn-around. The moderately simple and physically small refresh-turn circuits that can be positioned in the space available have been found to be unsatisfactory in that they are extremely sensitive to threshold voltage variations across the chip; and the more complicated refresh-turn circuits required for reliable operation are physically too large for the space available. There are numerous well known circuit designs available which will perform these functions of refresh-turn; however, practical considerations for integrating these larger space requirement circuits on the chip together with the CCD (charge-coupled-device) shift registers severely limits the possibility of their use. Such practical considerations include size, speed, power dissipation, number of clocking signals, bias voltages and compatibility with CCD processing. Of these, one of the most restrictive requirements is the size requirement. If more space were available, more complex circuits could be used and the other considerations taken care of. It is this problem of providing needed space that this invention solves by disclosing a novel structure that provides the space for the more complicated refresh-turn circuits that provides reliable and improved operation of the charge-coupled-device. Typical examples representative of the prior art in this field are U.S. Pat. Nos. 3,641,360 to patentee Y. L. Yao, 3,644,750 to patentee D. Campbell, 3,683,203 to patentee K. F. Smith, 3,764,824 to patentee F. L. J. Sangster, and 3,795,829 to patentee J. D. Wilcock.